Magnetoresistive random-access memory (“MRAM”) is a non-volatile memory technology that stores data through magnetic storage elements. These elements are two ferromagnetic plates or electrodes that can hold a magnetic field and are separated by a non-magnetic material, such as a non-magnetic metal or insulator. This structure is known as a magnetic tunnel junction (MTJ).
MRAM devices can store information by changing the orientation of the magnetization of the free layer of the MTJ. In particular, based on whether the free layer is in a parallel or anti-parallel alignment relative to the reference layer, either a one or a zero can be stored in each MRAM cell. Due to the spin-polarized electron tunneling effect, the electrical resistance of the cell change due to the orientation of the magnetic fields of the two layers. The electrical resistance is typically referred to as tunnel magnetoresistance (TMR) which is a magnetoresistive effect that occurs in a MTJ. The cell's resistance will be different for the parallel and anti-parallel states and thus the cell's resistance can be used to distinguish between a one and a zero. One important feature of MRAM devices is that they are non-volatile memory devices, since they maintain the information even when the power is off.
MRAM devices are considered as the next generation structures for a wide range of memory applications. MRAM products based on spin torque transfer switching are already making its way into large data storage devices. Spin transfer torque magnetic random access memory (STT-MRAM), or spin transfer switching, uses spin-aligned (polarized) electrons to change the magnetization orientation of the free layer in the magnetic tunnel junction. In general, electrons possess a spin, a quantized number of angular momentum intrinsic to the electron. An electrical current is generally unpolarized, e.g., it consists of 50% spin up and 50% spin down electrons. Passing a current though a magnetic layer polarizes electrons with the spin orientation corresponding to the magnetization direction of the magnetic layer (e.g., polarizer), thus produces a spin-polarized current. If a spin-polarized current is passed to the magnetic region of a free layer in the MTJ device, the electrons will transfer a portion of their spin-angular momentum to the magnetization layer to produce a torque on the magnetization of the free layer. Thus, this spin transfer torque can switch the magnetization of the free layer, which, in effect, writes either a one or a zero based on whether the free layer is in the parallel or anti-parallel states relative to the reference layer.
The fabrication of MRAM involves the formation of small MTJ (Magnetic Tunnel Junction) patterns in pillar shapes. The pillars or pillar structures can be patterned on a hard mask layer and then transferred to MTJ films. The patterning of pillars on a hard mask layer is traditionally done using an electron beam lithography in a research environment. However, for high volume production, electron beam patterning is not cost effective as the process is very slow. Alternately, these pillars can be patterned using optical lithography tools. Optical lithography resolution is limited by diffraction. Since the pillars, when printed onto a layer of photoresist, are two dimensional features, it is more challenging to achieve the same resolution as the resolution can be achieved by an 1D pattern such as a line.
Currently, MRAM devices are reported at 28 nm node with a bitcell size of, for example, 0.12 μm2. Although active MTJ pillar size can be reduced well below 100 nm, the pitch between MTJ devices is limited by individual bitcell size. Consequently, the pitch between CMOS bitcells need to be much larger than the achievable pitch between active MTJ device pillars. This hinders developing a high density MRAM memory with smaller active MTJ device arrays at higher density. With current research to develop, for example, sub 50 nm active MTJ devices, it will become difficult to have a test platform to test state of the art MTJ devices.
Thus what is needed is a fabrication process that will produce a state-of-the-art high density MTJ pillar array to create a test platform to test state of the art MTJ devices. What is further needed is a fabrication process that will produce a state-of-the-art high density MTJ pillar array. Additionally, existing CMOS design configurations need to be utilized without having to invest to develop new CMOS test platform fabrication processes.